In order to reduce the back end of line (BEOL) interconnect portion of a circuit delay, a conventional silicon dioxide dielectric (k of approximately 4.0) has been replaced with dense lower-k films with a k value of approximately 3.0. However, for further performance improvements, more dielectric capacitance reduction is required (k<2.5) for advanced devices.
Capacitance improvements can be made with porous low k dielectrics; however, porous low k dielectric materials have relatively weak mechanical properties as compared to dense dielectrics. It is also a significant challenge for the current BEOL process to integrate these porous low k dielectrics with other module processes. For example, the conventional chemical mechanical process (CMP) has difficulty polishing a low mechanical-module porous dielectric.
By way of further explanation, in conventional methods, a dielectric is deposited on a substrate. In known methods, the dielectric may be, for example, SiLK, SiCOH, SiO2, etc. The dielectric is patterned using conventional lithography and etching processes. A diffusion layer is lined into the patterned dielectric. The diffusion layer may be, for example, a Cu diffusion barrier consisting of Ta(N), Ti(N) or Ru(N). An interconnect structure is then deposited over the diffusion barrier (e.g., liner). The interconnect may consist of any conventional material such as, for example, Cu, Al, Cu(Al). After removing extra interconnect material by chemical-mechanical-polishing (CMP), a capping layer is then deposited over the structure, including over the interconnect itself. The capping layer may be any conventional capping layer such as, for example, Si3N4, SiC, SiC(N,H). Thereafter, dense dielectric material containing porogens such as, for example, p-SiCOH, is deposited on the structure.
In further steps, a UV cure is performed to burn out the porogens inside the entire dense dielectric material and transform the entire dense dielectric material to “porous”. However, by making the entire dense dielectric material porous, the structure presents weak mechanical properties inside the final interconnect structure. In further processing steps, conventional patterning including lithography and etching processes is performed to make vias electrically connected to the underneath interconnect. Conventional metallization and CMP processes are performed, e.g., the interconnect feature is lined with a conventional Cu diffusion barrier and a conductive material such as, for example, Cu, Al, Cu(Al) is filled within the remaining feature.